As the capacity of semiconductor memory continues to increase, attaining a sufficiently high yield becomes more difficult. To attain higher memory capacity, the area of a memory chip can be increased to accommodate a greater number of memory cells. Alternately, the density of the chip can be increased. Increasing the density involves reducing the size and increasing the quantity of memory cells on the chip, which leads to a proportional increase in defects.
To improve the yield, a number of techniques may be employed to fix or to compensate for the defects. A relatively expensive technique that is commonly used for repairing standard memory chips is a wafer test, sort and repair process. The capital equipment costs for burn-in and test facilities are relatively high, which can be amortized when the standard memory chips are produced in sufficiently large quantities. For lower production quantities, the amortized capital equipment costs often exceed the cost of scrapping the defective chips.
Embedded memory devices also face problems with attaining sufficient chip yield. Embedded memory devices combine logic and memory on a single silicon wafer and are not usually manufactured in large quantities. The wafer sort/test fixtures, burn-in fixtures, and repair facilities that are typically used with large quantity standard memory devices are not economically feasible. When a defect occurs on an embedded device, the device is typically scrapped.
Embedded devices typically have more defects per unit of memory than standard memory. This is due in part to the fact that the processing technology that is used for the logic is typically not compatible with the processing technology that is used for the memory. The majority of defects in an embedded device occur in the memory since most of the chip area is used for the memory. Typically, the prime yield is about 20% for conventional logic devices.
Referring now to FIG. 1, systems on chip (SOC) 10 typically include both logic 12 and embedded memory 14 that are fabricated on a single wafer or microchip. For example, the SOC 10 may be used for a disk drive and include read channels, a hard disk controller, an Error Correction Coding (ECC) circuit, high speed interfaces, and system memory. The logic 12 may include standard logic module(s) that are provided by the manufacturer and/or logic module(s) that are designed by the customer. The embedded memory 14 typically includes static random access memory (SRAM), dynamic random access memory (DRAM), and/or nonvolatile memory such as flash memory.
Referring now to FIG. 2, low chip yield is due in part to the small size of the memory cells in the embedded memory 14. The small memory cells are used to reduce the chip size and lower cost. Typical defects include random single bit failures that are depicted at 16. For a 64 Mb memory module, on the order of 1000 random single bit failures 16 may occur. Other defects include bit line defects that are depicted at 18 and 20. While bit and word line defects occur less frequently than the random single bit failures 16, they are easier and less costly to fix.
Referring now to FIG. 3, the embedded memory 14 typically includes a random data portion 24 and a cache data portion 26. Bits that are stored in the random data portion 24 are accessed individually. In contrast, bits that are stored in the cache data portion 26 are accessed in blocks having a minimum size such as 16 or 64 bits.
To improve reliability, an error correction coding (ECC) circuit 28 may be used. ECC coding bits 30 are used for ECC coding. For example, 2 additional bits are used for 16 bits and 8 additional bits are used for 64 bits. The ECC circuit 28 requires the data to be written to and read from the embedded memory 14 in blocks having the minimum size. Therefore, the ECC circuit 28 and error correction coding/decoding cannot be used for the random data portion 24. When accessing the random data portion 24, the ECC coding circuit 28 is disabled as is schematically illustrated at 32. ECC coding bits also increase the cost of fabricating the memory and reduce access times.
Because each of the bits in the random data portion 24 can be read individually, single bit failures in the random data portion 24 are problematic. During the wafer sort tests, if single bit failures are detected in the random data portion 24, repair of the SOC 10 must be performed, which significantly increases the cost of the SOC 10.